Integrated circuit technologies continue to evolve at a frantic pace. Computing and communications designs are incorporating more functionality, higher processing and transmission speeds, smaller feature sizes, more memory, etc., into smaller and more robust architectures.
SRAM memories may be used for high speed data storage inside modern microprocessors. Two significant results of continuing integrated circuit technology scaling are smaller transistor size, and more transistors per chip. Each of these features limits the lowest operating voltage (Vccmin) for SRAM memories.
As transistors become smaller, their relative variability increases, making matching of transistors more difficult. A number of physical reasons cause the variability to increase for smaller transistor size. For example, as the transistors become smaller, random dopant fluctuation and patterning control both become relatively larger.
Matching of transistors is critical for data stability in a 6-T SRAM bit cell, as any asymmetry leads to easier loss of data. Thus the likelihood of device mismatch for smaller cell size increases the Vccmin of the SRAM.
As SRAM bit density increases for a given chip area, the memory array size on the chip increases. Larger memory sizes involve more memory bits, therefore the mismatch problem between transistors is multiplied. As the array size increases, the chance for getting a bit with a large mismatch on a die increases. Since the Vccmin of the array is the highest value for any of the bits in the array, the array Vccmin increases with array size.
Together the two reasons stated above lead to an increase in the Vccmin with each technology generation. The first trend is unavoidable as smaller cell size is the main advantage of technology scaling. We describe here a method and apparatus to address the issue of increasing Vccmin with larger array size.